Chehine Melki
FPGA & RTL Design Engineer
Computer engineer specializing in synthesizable VHDL and RTL design, with proven expertise in timing-closed FPGA implementations and embedded firmware development across Xilinx and Intel toolchains.
Skills
At a glance
3
internships in hardware & firmware
171 MHz
timing closure on Quartus Prime
2-cycle
decode latency (ITCH feed handler)
Work Experience
Embedded Software Engineer Intern
Enda Tao, Tunis · Feb 2025 – Aug 2025
Developed and maintained C/C++ firmware for payment terminal hardware, debugging at the hardware level in a constrained embedded environment and integrating firmware modules with the payment services stack.
POS Security Research Intern
STB Bank, Tunis · Sep 2024 – Oct 2024
Conducted security research on point-of-sale hardware, analysing attack surfaces and documenting findings to inform hardening strategies for POS deployments.
FPGA / Digital Design Intern
General Electric, Radès, Tunis · Jun 2023 – Jul 2023
Contributed to VHDL RTL design using Xilinx Vivado, running functional simulations and bench-level checks to support design validation.
FPGA & RTL Projects
NASDAQ ITCH 5.0 Feed Handler
Designed a 64-bit AXI-Stream feed handler decoding NASDAQ TotalView-ITCH 5.0 over MoldUDP64/UDP/IPv4 with 2-cycle decode latency and downstream backpressure support. Achieved timing closure on both Quartus Prime (171 MHz, Cyclone 10 GX) and Vivado (Artix UltraScale+), verified across multiple ModelSim scenarios.
Pipelined RISC Microprocessor & ALU
Designed and synthesized a pipelined RISC microprocessor in VHDL on Xilinx FPGA, validating a 2K-instruction workload and implementing a combinational 4×4-digit BCD multiplier for the ALU datapath with comprehensive ModelSim testbenches covering pipeline hazards.
Key Strengths
- Proficient in synthesizable VHDL with hands-on experience in pipelining, FSMs, and AXI-Stream interfaces
- Expertise in timing closure and design verification across Xilinx Vivado and Intel Quartus Prime toolchains
- Strong foundation in computer architecture, RISC design, and market data protocols (ITCH/MoldUDP64)
- Comfortable with low-level embedded firmware debugging and hardware-software integration